Extremely thin Silicon-On-Insulator (ETSOI) planar Metal Oxide Silicon Field Effect Transistors (MOSFETs) are desirable for many aspects. Such structures provide fully depleted devices having planar architectures with superior short channel control, low junction leakage current, and an un-doped body with low variability from random dopant fluctuations. Thin body semiconductor devices have limitations, however, in that they are not well adapted for stress inducement in the channel (or body) for carrier mobility enhancement. Also, source/drain resistance tends to be too high due to thin Silicon (Si) layer (i.e., small amount of Si materials) for many applications.
In one proposed solution for inducing stress to a channel and reducing source/drain resistance, the structure of raised sources and drains can be formed using Si epitaxial growth. However, the added stress in a channel of a MOSFET on ETSOI by using such methods can still be minimal and the source and drain resistance is still too high for many applications which typically employ MOSFETs formed on a bulk Si substrate.